? 2003 microchip technology inc. advance information ds39617a-page 1 pic18f2455/2550/4455/4550 universal serial bus features: ? usb v2.0 compliant sie low-speed (1.5 mb/s) and full-speed (12 mb/s) supports control, interrupt, isochronous and bulk transfers supports up to 32 endpoints (16 bidirectional) 1-kbyte dual access ram for usb on-board usb transceiver with on-chip voltage regulator interface for off-chip usb transceiver streaming parallel port (spp) for usb streaming transfers (40/44-pin devices only) power managed modes: run: cpu on, peripherals on idle: cpu off, peripherals on sleep: cpu off, peripherals off idle mode currents down to 5.8 a typical sleep current down to 0.1 a typical timer1 oscillator: 1.1 a typical, 32 khz, 2v watchdog timer: 2.1 a typical two-speed oscillator start-up flexible oscillator structure: five crystal modes, including high-precision pll for usb two external rc modes, up to 4 mhz two external clock modes, up to 40 mhz internal oscillator block: - 8 user selectable frequencies, from 31 khz to 8 mhz - user tunable to compensate for frequency drift secondary oscillator using timer1 @ 32 khz fail-safe clock monitor - allows for safe shutdown if any clock stops peripheral highlights: high current sink/source: 25 ma/25 ma three external interrupts four timer modules (timer0 to timer3) up to 2 capture/compare/pwm (ccp) modules: - capture is 16-bit, max. resolution 6.25 ns (t cy /16) - compare is 16-bit, max. resolution 100 ns (t cy ) - pwm output: pwm resolution is 1 to 10-bit enhanced capture/compare/pwm (eccp) module: - multiple output modes - selectable polarity - programmable dead-time - auto-shutdown and auto-restart addressable usart module: - lin bus support master synchronous serial port (mssp) module supporting 3-wire spi? (all 4 modes) and i 2 c? master and slave modes 10-bit, up to 13-channels analog-to-digital converter module (a/d) with programmable acquisition time dual analog comparators with input multiplexing special microcontroller features: c compiler optimized architecture with optional extended instruction set 100,000 erase/write cycle enhanced flash program memory typical 1,000,000 erase/write cycle data eeprom memory typical flash/data eeprom retention: > 40 years self-programmable under software control priority levels for interrupts 8 x 8 single cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 41 ms to 131s programmable code protection single-supply 5v in-circuit serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins wide operating voltage range (2.0v to 5.5v) device program memory data memory i/o 10-bit a/d (ch) ccp/ eccp (pwm) spp mssp eausart comparators timers 8/16-bit flash (bytes) # single- word instructions sram (bytes) eeprom (bytes) spi master i 2 c pic18f2455 24k 12288 2048 256 24 10 2/0 no y y 1 2 1/3 pic18f2550 32k 16384 2048 256 24 10 2/0 no y y 1 2 1/3 pic18f4455 24k 12288 2048 256 35 13 1/1 yes y y 1 2 1/3 pic18F4550 32k 16384 2048 256 35 13 1/1 yes y y 1 2 1/3 28/40/44-pin high-performance, enhanced flash usb microcontrollers with nanowatt technology
pic18f2455/2550/4455/4550 ds39617a-page 2 advance information ? 2003 microchip technology inc. pin diagrams rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0/csspp rb3/an9/ccp2*/vpo rb2/an8/int2/vmo rb1/an10/int1/sck/scl rb0/an12/int0/sdi/sda v dd v ss rd7/spp7/p1d rd6/spp6/p1c rd5/spp5/p1b rd4/spp4 rc7/rx/dt/sdo rc6/tx/ck d+/vp d-/vm rd3/spp3 rd2/spp2 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/c vref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out re0/ck1spp/an5 re1/ck2spp/an6 re2/oespp/an7 av dd av ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2*/uoe rc2/ccp1/p1a v usb rd0/spp0 rd1/spp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4455 40-pin pdip pic18F4550 pic18f2550 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t13cki rc1/t1osi/ccp2*/uoe rc2/ccp1 v usb rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0/rcv rb3/an9/ccp2*/vpo rb2/an8/int2/vmo rb1/an10/int1/sck/scl rb0/an12/int0/sdi/sda v dd v ss rc7/rx/dt/sdo rc6/tx/ck d+/vp d-/vm 28-pin sdip, soic pic18f2455 note: pinouts are subject to change. * assignment of this feature is dependent on device configuration.
? 2003 microchip technology inc. advance information ds39617a-page 3 pic18f2455/2550/4455/4550 pin diagrams (continued) 44-pin qfn 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4455 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm nc rc6/tx/ck d+/vp d-/vm rd3/ssp3 rd2/ssp2 rd1/ssp1 rd0/ssp0 v usb rc2/ccp1/p1a rc1/t1osi/ccp2*/uoe rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss av dd ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out rc7/rx/dt/sdo rd4/ccp2*/p2a rd5/ssp5/p1b rd6/ssp6/p1c v ss v dd rb0/an12/int0/sdi rb1/an10/int1/sck/scl rb2/an8/int2/vmo rb3/an9/ccp2*/vpo rd7/ssp7/p1d 5 4 av ss v dd av dd 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4455 37 ra3/an3/v ref + ra1/an1 mclr /v pp /re3 nc nc rc6/tx/ck nc nc rc0/t1oso/t13cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out v ss v dd 44-pin tqfp 5 4 pic18F4550 rc7/rx/dt/sdo rd4/spp4 rd5/spp5/p1b rd6/spp6/p1c rd7/spp7/p1d rb0/an12/int0/sdi/sda rb1/an10/int1/sck/scl rb2/an8/int2/vmo rb3/an9/ccp2*/vpo rc1/t1osi/ccp2*/uoe rc2/ccp1/p1a v usb rd0/spp0 rd1/spp1 rd2/spp2 rd3/spp3 d-/vm d+/vp rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd ra0/an0 ra2/an2/v ref -/c vref note: pinouts are subject to change. * assignment of this feature is dependent on device configuration. pic18F4550 rb4/an11/kbi0/csspp re0/ck1spp/an5 re1/ck2spp/an6 re2/oespp/an7 rb4/an11/kbi0/csspp re0/ck1spp/an5 re1/ck2spp/an6 re2/oespp/an7
pic18f2455/2550/4455/4550 ds39617a-page 4 advance information ? 2003 microchip technology inc. notes:
ds39617a-page 5 advance information ? 2003 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. accuron, application maestro, dspicdem, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in- circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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